![]() ![]() ![]() As depicted in Figure C.1, select the example verilog project (Quartus II project files have the filename extension. C.1 Implementing a Circuit in a MAX 7000 CPLD Select File | Open Project and browse to the directory designstyle 2, which contains the Verilog design example used in Tutorial 1. To illustrate the procedures involved, we will first implement the example verilog project created in Tutorial 1 in a MAX 7000 CPLD. In addition to the modules used in Tutorial 1, the following Quartus II modules are introduced: Fitter, Floorplan Editor, and Timing Analyzer. Appendix C Tutorial 2 - Implementing Circuits in Altera Devices In this tutorial we describe how to use the physical design tools in Quartus II. ![]()
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January 2023
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